1. Field of the Invention
The present invention relates to a semiconductor device and fabrication method thereof, and more particularly, to a semiconductor device having a landing pad and a fabrication method thereof.
2. Description of Related Art
Generally, semiconductor memory devices can be classified into volatile memory devices and nonvolatile memory devices. The volatile memory devices include a DRAM (Dynamic RAM) and a SRAM (Static RAM). Generally, the DRAM has an integration density higher than the SRAM, which is the reason that the DRAM has been widely used as a memory device for a computer. A unit cell on the cell array region of the DRAM includes a single cell capacitor and a single access transistor.
In response to the increase in the integration density of the DRAM, a DRAM cell having a structural configuration comprising a capacitor over bit line (COB) has been widely employed in order to increase the capacitance of a DRAM capacitor. In this structural configuration, more specifically, the cell capacitor is placed above the bit line. Therefore, the more the integration density of the DRAM is increased, the more difficult it is to form a storage node contact hole for connecting the storage node (lower electrode) of the cell capacitor to the source region of the access transistor.
Recently, in order to increase the ease of formation of the storage node contact hole in a semiconductor fabrication process, a landing pad has been widely employed. The landing pad is interposed between the storage node and the source region.
FIGS. 1 through 4 illustrate a method of forming DRAM cells having landing pads according to the conventional prior art.
Referring to FIG. 1, a trench isolation layer 3 is formed on an active region 3a of a semiconductor substrate 1. A gate insulating layer 5 is also formed on the active region 3a. A conductive layer and a capping layer are sequentially formed on the overall surface of the semiconductor substrate having a gate insulating layer 5. The capping layer and the conductive layer are etched to form a plurality of word line patterns 10 across the upper part of the active region 3a. Accordingly, each of the word lines patterns 10 includes a word line (gate electrode) 7 and a capping layer pattern 9 stacked thereon. Impurity ions are implanted in the active region 3a of the semiconductor substrate 1 using the word line pattern 10 and the trench isolation layer 3 as ion implantation masks to form a first and a second source region 11s′, 11s″ together with one common drain region 11d. Spacers 13 are formed on the side walls of the word line patterns 10. The capping layer patterns 9 and the spacers 13 are formed of a silicon nitride layer.
Referring to FIG. 2, an interlayer insulating layer 15 is formed on the overall surface of the semiconductor substrate. Then, a bit line pad contact hole 17d, and first and second storage node pad contact holes 17s′, 17s″, are formed in the interlayer insulating layer 15 to expose the common drain region 11d and the first and the second source regions 11s′, 11s″, respectively. The interlayer insulating layer 15 is generally formed of a silicon oxide layer. During the formation of the pad contact holes 17d, 17s′, 17s″, the capping layer pattern 9 and the spacers 13 function as an etching stop layer. At this time, separation layers 15a, which are formed from the interlayer insulating layer 15, are formed between the pad contact holes 17d, 17s′, 17s″. 
Referring to FIG. 3, in order to remove the polymer and the natural oxide layer remaining inside the pad contact holes 17d, 17s′, 17s″, an oxide layer etching solution is applied on the semiconductor substrate 1 to clean the inside portions of the pad contact holes 17d, 17s′, 17s″. As a result, the width of the separation layer 15a is reduced. In the event that the cleaning process is performed for an extended time, or for several times, a through hole 15a″ may be formed in a predetermined region of the separation layers 15a, or alternatively, the separation layers 15a can be removed. Then, a conductive layer 19 is formed on the overall surface of the semiconductor substrate having the through hole 15a″. 
Referring to FIG. 4, the conductive layer 19 is planarized to expose the upper surface of the interlayer insulating layer 15, and to form a bit line pad 19d, a first storage node pad 19s′ and a second storage node pad 19s″. The bit line pad 19d, the first storage node pad 19s′ and the second storage node pad 19s″ are called “landing pads”. If the cleaning process is performed severely, the landing pads 19d, 19s′, 19s″ are connected to one another as shown in FIG. 4. As described above, it has been difficult to perform the cleaning process of the prior art sufficiently enough to remove the polymer and the natural oxide layer before forming the landing pads. That is, since the severity of the cleaning process is reduced, it is difficult to improve the contact resistance of each of the landing pads.
On the other hand, U.S. Pat. No. 6,117,757 to Chuan-fu Wang and Benjamin Szu-Min Lin (“U.S. '757”) is related to a method of forming landing pads for bit line and node contact. As set forth in U.S. '757, gate patterns having a multi-layer are formed on the semiconductor substrate, and first spacers are formed on the side walls of the gate patterns. Next, a first dielectric layer is deposited on the semiconductor substrate having the gate patterns and the first spacers. Contact openings are then formed in the first dielectric layer using a self-aligned method to expose the semiconductor substrate. Next, a second dielectric layer is conformally formed on the overall surface of the semiconductor substrate, and the second dielectric layer is etched back to form second spacers on the side walls of the contact openings. Subsequently, a conductive layer is formed on the overall surface of the semiconductor substrate and patterned to expose the upper portions of the second spacers and to form bit lines and landing pads.
However, with the pitch of the gate patterns being fixed, the formation of the second spacers causes the width of the contact opening to be narrowed. Thus, the contact resistance is increased between the bit lines and the semiconductor substrate, together with between the landing pads and the semiconductor substrate. Furthermore, the method of U.S. '757 may cause a short circuit between the bit lines and the landing pads as the design rule of the semiconductor device is further reduced.